FreeRTOS V11.3.0 on a LiteX VexRiscv SoC: unmodified upstream kernel, a thin LiteX-side port (timer0 tick, IRQ dispatch, UART stream buffer), a two-phase litex_sim harness that iterates in seconds, and the same firmware.bin on an Arty A7.
LiteX on the Trenz TEL0025: a Certus-NX with 32 MB of HyperRAM as main memory, a HyperRAM core optimization pass that took writes from 5.2 to 46.7 MiB/s, and Linux 6.9 booting on top.
Describe the SoC in Python, then run Python on it. The MicroPython-on-LiteX port, from its Fupy origins to a fresh rebase onto upstream MicroPython 1.28, with networking, SD and SPI-flash storage across 150+ boards.
JavaScript running bare-metal on a RISC-V softcore inside a LiteX SoC, with framebuffer demos and a live browser editor served straight from the FPGA. No host, no transpilation.
