Our own open AD9361 SDR in an M.2 form factor, built on LiteX. Why we kept the ordinary RFIC, the transports (PCIe, Ethernet, SATA), the White Rabbit timing work, and what’s next.
Describe the SoC in Python, then run Python on it. The MicroPython-on-LiteX port, from its Fupy origins to a fresh rebase onto upstream MicroPython 1.28, with networking, SD and SPI-flash storage across 150+ boards.
A $15 ColorLight ECP5 board, a LiteX SoC with Ethernet, and a cheap relay module: remote power-on/off for an office PC during COVID, built with the fully open-source Yosys/NextPnr toolchain. With a note on reversing boards from the FPGA side.