Fpga

LiteX on the Trenz TEL0025: a Certus-NX with 32 MB of HyperRAM as main memory, a HyperRAM core optimization pass that took writes from 5.2 to 46.7 MiB/s, and Linux 6.9 booting on top.

MicroPython on the Forgix’s RP2350 loads the Efinix bitstream and drives LiteX CSRs over 3-wire SPIBone. No softcore, no flash storage: the MCU owns the bus.

Our own open AD9361 SDR in an M.2 form factor, built on LiteX. Why we kept the ordinary RFIC, the transports (PCIe, Ethernet, SATA), the White Rabbit timing work, and what’s next.

Describe the SoC in Python, then run Python on it. The MicroPython-on-LiteX port, from its Fupy origins to a fresh rebase onto upstream MicroPython 1.28, with networking, SD and SPI-flash storage across 150+ boards.

A $15 ColorLight ECP5 board, a LiteX SoC with Ethernet, and a cheap relay module: remote power-on/off for an office PC during COVID, built with the fully open-source Yosys/NextPnr toolchain. With a note on reversing boards from the FPGA side.

JavaScript running bare-metal on a RISC-V softcore inside a LiteX SoC, with framebuffer demos and a live browser editor served straight from the FPGA. No host, no transpilation.

LiteX was always command-line and text first, for cost reasons. It turns out that’s exactly what an AI agent needs to drive an FPGA. Here’s the methodology we use now, with LiteNVMe and M2SDR as real examples.

PR #2468 lets LiteX run the CPU in QEMU while Verilator keeps simulating the SoC. Here’s how it works, a first benchmark, and a real rv64 Linux boot.