The Elgato Cam Link 4K, from a 2019 LiteX board that booted Linux as a DRAM test to a complete open capture card: what the design does, how ECP5 DDR3 got twice the bandwidth in LiteDRAM, why it has lower latency than the stock firmware, and what changed between the two attempts.
The Chromatic’s ESP32 as an SDR: ESP-SDR on the radio side, the FPGA and a RISC-V on the console side, and a USB link to SoapySDR. How the samples move, how the tuning was pushed from the Wi-Fi channels to 1775-2890 MHz, the decoding tools running on the softcore, and what the result can and cannot do.
Doom on the ModRetro Chromatic with a VexRiscv in the GW5A-25 and 7.5 MB of PSRAM as main RAM: how the LiteX design made the port quick, and the measured ladder of gateware, compiler and renderer changes that took it from 6.4 to 31 fps.
How we moved the ModRetro Chromatic FPGA from a Gowin project with encrypted IP to an all-open LiteX design, one block at a time and never broken on hardware, and what it gave back to LiteX: a soft USB 2.0 PHY, an OPI PSRAM core and a new board target.
The full story of LiteSATA’s ECP5 PHY: four years parked on issue #27, one weekend of AI bring-up to first link-up, one very silly bench bug, and three merged PRs. What AI-assisted FPGA engineering looks like when it works, effort included.
FreeRTOS V11.3.0 on a LiteX VexRiscv SoC: unmodified upstream kernel, a thin LiteX-side port (timer0 tick, IRQ dispatch, UART stream buffer), a two-phase litex_sim harness that iterates in seconds, and the same firmware.bin on an Arty A7.
LiteX on the Trenz TEL0025: a Certus-NX with 32 MB of HyperRAM as main memory, a HyperRAM core optimization pass that took writes from 5.2 to 46.7 MiB/s, and Linux 6.9 booting on top.
MicroPython on the Forgix’s RP2350 loads the Efinix bitstream and drives LiteX CSRs over 3-wire SPIBone. No softcore, no flash storage: the MCU owns the bus.
Our own open AD9361 SDR in an M.2 form factor, built on LiteX. Why we kept the ordinary RFIC, the transports (PCIe, Ethernet, SATA), the White Rabbit timing work, and what’s next.
Describe the SoC in Python, then run Python on it. The MicroPython-on-LiteX port, from its Fupy origins to a fresh rebase onto upstream MicroPython 1.28, with networking, SD and SPI-flash storage across 150+ boards.
