The full story of LiteSATA’s ECP5 PHY: four years parked on issue #27, one weekend of AI bring-up to first link-up, one very silly bench bug, and three merged PRs. What AI-assisted FPGA engineering looks like when it works, effort included.
LiteX on the Trenz TEL0025: a Certus-NX with 32 MB of HyperRAM as main memory, a HyperRAM core optimization pass that took writes from 5.2 to 46.7 MiB/s, and Linux 6.9 booting on top.
Our own open AD9361 SDR in an M.2 form factor, built on LiteX. Why we kept the ordinary RFIC, the transports (PCIe, Ethernet, SATA), the White Rabbit timing work, and what’s next.
