FreeRTOS V11.3.0 on a LiteX VexRiscv SoC: unmodified upstream kernel, a thin LiteX-side port (timer0 tick, IRQ dispatch, UART stream buffer), a two-phase litex_sim harness that iterates in seconds, and the same firmware.bin on an Arty A7.
MicroPython on the Forgix’s RP2350 loads the Efinix bitstream and drives LiteX CSRs over 3-wire SPIBone. No softcore, no flash storage: the MCU owns the bus.
Describe the SoC in Python, then run Python on it. The MicroPython-on-LiteX port, from its Fupy origins to a fresh rebase onto upstream MicroPython 1.28, with networking, SD and SPI-flash storage across 150+ boards.
A $15 ColorLight ECP5 board, a LiteX SoC with Ethernet, and a cheap relay module: remote power-on/off for an office PC during COVID, built with the fully open-source Yosys/NextPnr toolchain. With a note on reversing boards from the FPGA side.
JavaScript running bare-metal on a RISC-V softcore inside a LiteX SoC, with framebuffer demos and a live browser editor served straight from the FPGA. No host, no transpilation.
