Hi, I’m Florent Kermarrec. I started LiteX and I’m its main developer at enjoy-digital, though by now it’s very much a community project, with a lot of people contributing cores, ports and fixes.
LiteX is an open-source framework that lets you build FPGA SoCs (CPUs, DRAM controllers, PCIe, Ethernet, all the fun stuff) in Python, and deploy them on more than a hundred boards. The motto has been the same from day one:
Build your hardware, easily!
This blog is where I write up things I’m experimenting with. Some are features landing in LiteX, some are detours, some are just me checking whether an idea actually works.
If you want to follow along or build something yourself:
- LiteX: https://github.com/enjoy-digital/litex
- enjoy-digital: https://github.com/enjoy-digital
- Chat: the LiteX community hangs out on Discord and IRC (
#litexon Libera). - Email: florent@enjoy-digital.fr
Everything here is open source and BSD-2-Clause, like LiteX itself.
The work and ideas here are my own. I write up the posts and draw the diagrams with AI in the loop, which I’ve come to think is just part of how RTL gets built now.
It also helps with a more practical constraint: I have four kids, I try to keep weekends for them, and my time is tight. Without a bit of help like this, the blog would probably just not exist. 🙂